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FEATURES 12-Bit Resolution Low Gain TC: 2 ppm/ C typ Fast TTL Compatible Data Latches Single +5 V to +15 V Supply Small 20-Lead 0.3" DIP and 20-Terminal Surface Mount Packages Latch Free (Schottky Protection Diode Not Required) Low Cost Ideal for Battery Operated Equipment
VREF 19
CMOS 12-Bit Buffered Multiplying DAC AD7545
FUNCTIONAL BLOCK DIAGRAM
RFB 20
AD7545
12-BIT MULTIPLYING DAC
R 1 2 OUT 1 AGND
12 WR 17 CS 16 INPUT DATA LATCHES 3 12 DGND 18 VDD
DB11-DB0 (PINS 4-15)
GENERAL DESCRIPTION
The AD7545 is a monolithic 12-bit CMOS multiplying DAC with onboard data latches. It is loaded by a single 12-bit wide word and directly interfaces to most 12- and 16-bit bus systems. Data is loaded into the input latches under the control of the CS and WR inputs; tying these control inputs low makes the input latches transparent, allowing direct unbuffered operation of the DAC.
The AD7545 is particularly suitable for single supply operation and applications with wide temperature variations. The AD7545 can be used with any supply voltage from +5 V to +15 V. With CMOS logic levels at the inputs the device dissipates less than 0.5 mW for VDD = +5 V.
PIN CONFIGURATIONS DIP
DGND
LCCC
DGND
AGND OUT 1
PLCC
AGND OUT 1
VREF
AGND 2 DGND 3 DB11 (MSB) 4 DB10 5 DB9 6 DB8 7 DB7 8 DB6 9 DB5 10
19 VREF 18 VDD 17 WR
RFB
OUT 1 1
20 RFB
3 DB11 (MSB) 4 DB10 5 DB9 6 DB8 7 DB7 8
2
1 20 19 18 VDD
3 DB11 (MSB) 4 DB10 5 DB9 6 DB8 7 DB7 8 9
DB6
2
1
20 19
PIN 1 IDENTIFIER
RFB
VREF
18 VDD 17 WR 16 CS 15 DB0 (LSB) 14 DB1
AD7545
16 CS
AD7545
TOP VIEW (Not to Scale)
17 WR 16 CS 15 DB0 (LSB) 14 DB1
AD7545
TOP VIEW (Not to Scale)
TOP VIEW 15 DB0 (MSB) (Not to Scale) 14 DB1 13 DB2
DB6
DB4
DB3
DB5
DB2
12 DB3 11 DB4
9 10 11 12 13
10 11 12 13
DB5 DB4 DB3 DB2
REV. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 World Wide Web Site: http://www.analog.com Fax: 617/326-8703 (c) Analog Devices, Inc., 1997
AD7545-SPECIFICATIONS (V
Parameter STATIC PERFORMANCE Resolution Version All J, A, S K, B, T L, C, U GL, GC, GU J, A, S K, B, T L, C, U GL, GC, GU J, A, S K, B, T L, C, U GL, GC, GU All All J, K, L, GL A, B, C, GC S, T, U, GU All 12 2 1 1/2 1/2 4 1 1 1 20 10 5 1 5 0.015 10 10 10 2
REF
= +10 V, VOUT1 = O V, AGND = DGND unless otherwise noted)
VDD = +15 V Limits TA = + 25 C TMIN, TMAX1 12 2 1 1/2 1/2 4 1 1 1 25 15 10 6 10 0.01 10 10 10 2 12 2 1 1/2 1/2 4 1 1 1 25 15 10 7 10 0.02 50 50 200 2
VDD = +5 V Limits TA = + 25 C TMIN, TMAX1 12 2 1 1/2 1/2 4 1 1 1 20 10 6 2 5 0.03 50 50 200 2
Units Bits LSB max LSB max LSB max LSB max LSB max LSB max LSB max LSB max LSB max LSB max LSB max LSB max ppm/C max % per % max nA max nA max nA max s max
Test Conditions/Comments
Differential Nonlinearity
Gain Error (Using Internal RFB) 2
10-Bit Monotonic TMIN to TMAX 12-Bit Monotonic TMIN to TMAX 12-Bit Monotonic TMIN to TMAX 12-Bit Monotonic TMIN to TMAX DAC Register Loaded with 1111 1111 1111 Gain Error Is Adjustable Using the Circuits of Figures 4, 5, and 6 Typical Value is 2 ppm/C for VDD = +5 V VDD = 5% DB0-DB11 = 0 V; WR, CS = 0 V
Gain Temperature Coefficient 3 Gain/Temperature DC Supply Rejection 3 Gain/VDD Output Leakage Current at OUT1
DYNAMIC PERFORMANCE Current Settling Time 3
To 1/2 LSB. OUT1 Load = 100 . DAC Output Measured from Falling Edge of WR, CS = 0.
Propagation Delay 3 (from Digital Input Change to 90% of Final Analog Output) Digital-to-Analog Glitch Inpulse AC Feedthrough5 At OUT1 REFERENCE INPUT Input Resistance (Pin 19 to GND) ANALOG OUTPUT Output Capacitance 3 COUT1 COUT1 DIGITAL INPUTS Input High Voltage VIH Input Low Voltage VIL Input Current6 IIN Input Capacitance3 DB0-DB11 WR, CS SWITCHING CHARACTERISTICS 7 Chip Select to Write Setup Time tCS Chip Select to Write Hold Time tCH Write Pulse Width tWR Data Setup Time tDS Data Hold Time tDH POWER SUPPLY IDD
All All All All
300 400 5 7 25
- - 5 7 25
250 250 5 7 25
- - 5 7 25
ns max nV sec typ mV p-p typ k min k max
OUT1 Load = 100 , CEXT = 13 pF4 VREF = AGND VREF = 10 V, 10 kHz Sinewave Input Resistance TC = -300 ppm/C typ Typical Input Resistance = 11 k
All
70 200
70 200
70 200
70 200
pF max pF max
DB0-DB11 = 0 V, WR, CS = 0 V DB0-DB11 = VDD, WR, CS = 0 V
All All All All All All
2.4 0.8 1 5 20 280 200 0 250 175 140 100 10 2 100 10
2.4 0.8 10 5 20 380 270 0 400 280 210 150 10 2 500 10
13.5 1.5 1 5 20 180 120 0 160 100 90 60 10 2 100 10
13.5 1.5 10 5 20 200 150 0 240 170 120 80 10 2 500 10
V min V max A max pF max pF max ns min ns typ ns min ns min ns typ ns min ns typ ns min mA max A max A typ All Digital Inputs VIL or VIH All Digital Inputs 0 V to VDD All Digital Inputs 0 V to VDD tCS tWR, tCH 0 VIN = 0 or VDD VIN = 0 VIN = 0 See Timing Diagram
All All All
All All
NOTES 1 Temperature range as follows: J, K, L, GL versions, 0C to +70C; A, B, C, GC versions, -25C to +85C; S, T, U GU versions, -55C to +125C. 2 This includes the effect of 5 ppm max gain TC. 3 Guaranteed but not tested. 4 DB0-DB11 = 0 V to VDD or VDD to 0 V. 5 Feedthrough can be further reduced by connecting the metal lid on the ceramic package (Suffix D) to DGND. 6 Logic inputs are MOS gates. Typical input current (+25C) is less than 1 nA. 7 Sample tested at +25C to ensure compliance. Specifications subject to change without notice.
-2-
REV. A
AD7545
tCS
CHIP SELECT
tCH
VDD 0 WRITE MODE:
MODE SELECTION HOLD MODE: EITHER CS OR WR HIGH, DATA BUS (DB0-DB11) IS LOCKED OUT; DAC HOLDS LAST DATA PRESENT WHEN WR OR CS ASSUMED HIGH STATE.
CS AND WR LOW, DAC RESPONDS TO DATA BUS (DB0-DB11) INPUTS.
tWR
WRITE
VDD 0
tDS
DATA IN (DB0-DB11) VIH VIL DATA VALID
tDH
VDD 0
NOTES: VDD = +5V; tr = tf = 20ns VDD = +15V; tr = tf = 40ns ALL INPUT SIGNAL RISE AND FALL TIMES MEASURED FROM 10% TO 90% OF VDD. TIMING MEASUREMENT REFERENCE LEVEL IS VIH + VIL/2.
Write Cycle Timing Diagram
ABSOLUTE MAXIMUM RATINGS*
(TA = + 25C unless otherwise noted) VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3, +17 V Digital Input Voltage to DGND . . . . . . . -0.3 V, VDD +0.3 V VRFB, VREF to DGND . . . . . . . . . . . . . . . . . . . . . . . . . 25 V VPIN1 to DGND . . . . . . . . . . . . . . . . . . . . -0.3 V, VDD +0.3 V AGND to DGND . . . . . . . . . . . . . . . . . -0.3 V, VDD + 0.3 V Power Dissipation (Any Package) to +75C . . . . . . . 450 mW Derates above +75C . . . . . . . . . . . . . . . . . . . . . . 6 mW/C Operating Temperature
Commercial (J, K, L, GL) Grades . . . . . . . . 0C to +70C Industrial (A, B, C, GC) Grades . . . . . . . . -25C to +85C Extended (S, T, U, GU) Grades . . . . . . . -55C to +125C Storage Temperature . . . . . . . . . . . . . . . . . . -65C to +150C Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . +300C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7545 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
TERMINOLOGY
RELATIVE ACCURACY
ORDERING GUIDE1
Maximum Gain Error TA = +25 C VDD = +5 V 20 LSB 20 LSB 20 LSB 10 LSB 10 LSB 10 LSB 5 LSB 5 LSB 5 LSB 1 LSB 1 LSB 1 LSB 20 LSB 20 LSB 10 LSB 10 LSB 5 LSB 5 LSB 1 LSB 1 LSB
The amount by which the D/A converter transfer function differs from the ideal transfer function after the zero and fullscale points have been adjusted. This is an endpoint linearity measurement.
DIFFERENTIAL NONLINEARITY
Model2 AD7545JN AD7545AQ AD7545SQ AD7545KN AD7545BQ AD7545TQ AD7545LN AD7545CQ AD7545UQ AD7545GLN AD7545GCQ AD7545GUQ AD7545JP AD7545SE AD7545KP AD7545TE AD7545LP AD7545UE AD7545GLP AD7545GUE
Temperature Range 0C to +70C -25C to +85C -55C to +125C 0C to +70C -25C to +85C -55C to +125C 0C to +70C -25C to +85C -55C to +125C 0C to +70C -25C to +85C -55C to +125C 0C to +70C -55C to +125C 0C to +70C -55C to +125C 0C to +70C -55C to +125C 0C to +70C -55C to +125C
Relative Accuracy 2 LSB 2 LSB 2 LSB 1 LSB 1 LSB 1 LSB 1/2 LSB 1/2 LSB 1/2 LSB 1/2 LSB 1/2 LSB 1/2 LSB 2 LSB 2 LSB 1 LSB 1 LSB 1/2 LSB 1/2 LSB 1/2 LSB 1/2 LSB
Package Options3 N-20 Q-20 Q-20 N-20 Q-20 Q-20 N-20 Q-20 Q-20 N-20 Q-20 Q-20 P-20A E-20A P-20A E-20A P-20A E-20A P-20A E-20A
The difference between the measured change and the ideal change between any two adjacent codes. If a device has a differential nonlinearity of less than 1 LSB it will be monotonic, i.e., the output will always increase for an increase in digital code applied to the D/A converter.
PROPAGATION DELAY
This is a measure of the internal delay of the circuit and is measured from the time a digital input changes to the point at which the analog output at OUT1 reaches 90% of its final value.
DIGITAL-TO-ANALOG GLITCH IMPULSE
This is a measure of the amount of charge injected from the digital inputs to the analog outputs when the inputs change state. It is usually specified as the area of the glitch in nV secs and is measured with VREF = AGND and an ADLH0032CG as the output op amp, C1 (phase compensation) = 33 pF.
NOTES 1 Analog Devices reserves the right to ship either ceramic (D-20) in lieu of cerdip packages (Q-20). 2 To order MIL-STD-883, Class B process parts, add /883B to part number. Contact local sales office for military data sheet. For U.S. Standard Military DRAWING (SMD) see DESC drawing 5962-87702. 3 E = Leadless Ceramic Chip Carrier; N = Plastic DIP; P = Plastic Leaded Chip Carrier; Q = Cerdip.
REV. A
-3-
AD7545
CIRCUIT INFORMATION--D/A CONVERTER SECTION
Figure 1 shows a simplified circuit of the D/A converter section of the AD7545 and Figure 2 gives an approximate equivalent circuit. Note that the ladder termination resistor is connected to AGND. R is typically 11 k.
VREF R R R R
power supply. To minimize power supply currents it is recommended that the digital input voltages be as close as practicably possible to the supply rails (VDD and DGND). The AD7545 may be operated with any supply voltage in the range 5 VDD 15 volts. With VDD = +15 V the input logic levels are CMOS compatible only, i.e., 1.5 V and 13.5 V.
BASIC APPLICATIONS
2R
2R
2R
2R
2R
2R
RFB OUT 1 AGND DB11 (MSB) DB10 DB9 DB1 DB0 (LSB)
Figure 1. Simplified D/A Circuit of AD7545
Figures 4 and 5 show simple unipolar and bipolar circuits using the AD7545. Resistor R1 is used to trim for full scale. The "G" versions (AD7545GLN, AD7545GCQ, AD7545GUD) have a guaranteed maximum gain error of 1 LSB at +25C (VDD = +5 V), and in many applications it should be possible to dispense with gain trim resistors altogether. Capacitor C1 provides phase compensation and helps prevent overshoot and ringing when using high speed op amps. Note that all the circuits of Figures 4, 5 and 6 have constant input impedance at the VREF terminal. The circuit of Figure 1 can either be used as a fixed reference D/A converter so that it provides an analog output voltage in the range 0 to -VIN (note the inversion introduced by the op amp), or VIN can be an ac signal in which case the circuit behaves as an attenuator (2-Quadrant Multiplier). VIN can be any voltage in the range -20 VIN + 20 volts (provided the op amp can handle such voltages) since VREF is permitted to exceed VDD. Table II shows the code relationship for the circuit of Figure 4.
VDD R2* 20 RFB OUT1 1 AGND DGND 3 ANALOG COMMON DB11-DB0 2 AD544L (SEE TEXT) C1 33pF VOUT
The binary weighted currents are switched between the OUT1 bus line and AGND by N-channel switches, thus maintaining a constant current in each ladder leg independent of the switch state. The capacitance at the OUT1 bus line, COUT1, is code dependent and varies from 70 pF (all switches to AGND) to 200 pF (all switches to OUT1). One of the current switches is shown in Figure 2. The input resistance at VREF (Figure 1) is always equal to RLDR (RLDR is the R/2R ladder characteristic resistance and is equal to value "R"). Since RIN at the VREF pin is constant, the reference terminal can be driven by a reference voltage or a reference current, ac or dc, of positive or negative polarity. (If a current source is used, a low temperature coefficient external RFB is recommended to define scale factor.)
TO LADDER
18 VIN R1* VDD 19 VREF
AD7545
FROM INTERFACE LOGIC
*REFER TO TABLE I
Figure 4. Unipolar Binary Operation
Table I. Recommended Trim Resistor Values vs. Grades for VDD = +5 V
AGND
OUT 1
Figure 2. N-Channel Current Steering Switch
CIRCUIT INFORMATION--DIGITAL SECTION
Trim Resistor R1 R2
J/A/S 500 150
K/B/T 200 68
L/C/U 100 33
GL/GC/GU 20 6.8
Figure 3 shows the digital structure for one bit. The digital signals CONTROL and CONTROL are generated from CS and WR.
TO AGND SWITCH VIN TO OUT1 SWITCH
Table II. Unipolar Binary Code Table for Circuit of Figure 4
Binary Number in DAC Register Analog Output
4095 -VIN 4096 2048 -VIN 4096 = -1/2 VIN 1 -VIN 4096 0 Volts
INPUT BUFFERS
1111
CONTROL CONTROL
1111
1111
Figure 3. Digital Input Structure
1000
0000
0000
The input buffers are simple CMOS inverters designed so that when the AD7545 is operated with VDD = 5 V, the buffers convert TTL input levels (2.4 V and 0.8 V) into CMOS logic levels. When VIN is in the region of 2.0 volts to 3.5 volts, the input buffers operate in their linear region and draw current from the -4-
0000 0000
0000 0000
0001 0000
REV. A
AD7545
Figure 5 and Table III illustrate the recommended circuit and code relationship for bipolar operation. The D/A function itself uses offset binary code and inverter U1 on the MSB line converts twos complement input code to offset binary code. If appropriate; inversion of the MSB may be done in software using an exclusive -OR instruction and the inverter omitted. R3, R4 and R5 must be selected to match within 0.01% and they should be the same type of resistor (preferably wire-wound or metal foil), so their temperature coefficients match. Mismatch of R3 value to R4 causes both offset and full-scale error. Mismatch of R5 and R4 and R3 causes full-scale error.
VDD R2* C1 33pF OUT1 1 A1 AGND DB11 4 U1 (SEE TEXT) DB10-DB0 2 AD544L R6 5k 10% 11 12 DATA INPUT ANALOG COMMON A2 VOUT AD544J R3 10k R4 20k R5 20k
Table IV. 12-Plus Sign Magnitude Code Table for Circuit of Figure 6
Sign Bit
Binary Number in DAC MSB LSB
Analog Output, VOUT
0 0 1 1
1111 1111 1111 0000 0000 0000 0000 0000 0000 1111 1111 1111
4095 + VIN x 4096 0 Volts 0 Volts 4095 - VIN x 4096
18 VDD 19 VREF VIN R1*
20 RFB
Note: Sign bit of "0" connects R3 to GND.
AD7545
APPLICATIONS HINTS
*FOR VALUES OF R1 AND R2
SEE TABLE I.
Figure 5. Bipolar Operation (Twos Complement Code)
Table III. Twos Complement Code Table for Circuit of Figure 5
Data Input 0111 1111 1111
Analog Output
2047 +VIN x 2048 1 +VIN x 2048
Output Offset: (CMOS D/A converters exhibit a code dependent output resistance which, in turn, causes a code dependent amplifier noise gain. The effect is a code dependent differential nonlinearity term at the amplifier output that depends on VOS where VOS is the amplifier input offset voltage. To maintain monotonic operation it is recommended that VOS be no greater than 25 x 10-6) (VREF) over the temperature range of operation. Suitable op amps are AD517L and AD544L. The AD517L is best suited for fixed reference applications with low bandwidth requirements: it has extremely low offset (50 V) and in most applications will not require an offset trim. The AD544L has a much wider bandwidth and higher slew rate and is recommended for multiplying and other applications requiring fast settling. An offset trim on the AD544L may be necessary in some circuits. General Ground Management: AC or transient voltages between AGND and DGND can cause noise injection into the analog output. The simplest method of ensuring that voltages at AGND and DGND are equal is to tie AGND and DGND together at the AD7545. In more complex systems where the AGND and DGND intertie is on the backplane, it is recommended that two diodes be connected in inverse parallel between the AD7545 AGND and DGND pins (IN914 or equivalent). Digital Glitches: When WR and CS are both low the latches are transparent and the D/A converter inputs follow the data inputs. In some bus systems, data on the data bus is not always valid for the whole period during which WR is low and as a result invalid data can briefly occur at the D/A converter inputs during a write cycle. Such invalid data can cause unwanted glitches at the output of the D/A converter. The solution to this problem, if it occurs, is to retime the write pulse WR so that it only occurs when data is valid. Another cause of digital glitches is capacitive coupling from the digital lines to the OUT1 and AGND terminals. This should be minimized by screening the analog pins of the AD7545 (Pins 1, 2, 19, 20) from the digital pins by a ground track run between Pins 2 and 3 and between Pins 18 and 19 of the AD7545. Note how the analog pins are at one end of the package and separated from the digital pins by VDD and DGND to aid screening at the board level. On-chip capacitive coupling can also give rise to crosstalk from the digital-to-analog sections of the AD7545, particularly in circuits with high currents and fast rise and fall times. This type of crosstalk is minimized by using -5-
0000 0000 1111
0000 0000 1111
0001 0000 1111
0 Volts
1 -VIN x 2048 2048 -VIN x 2048
1000
0000
0000
Figure 6 shows an alternative method of achieving bipolar output. The circuit operates with sign plus magnitude code and has the advantage of giving 12-bit resolution in each quadrant, compared with 11-bit resolution per quadrant for the circuit of Figure 5. The AD7592 is a fully protected CMOS change-over switch with data latches. R4 and R5 should match each other to 0.01% to maintain the accuracy of the D/A converter. Mismatch between R4 and R5 introduces a gain error.
VDD R2* C1 33pF OUT1 1 A1 AGND 2 DB11-DB0 AD544L 3 ANALOG COMMON R4 20k R3 10k 10% 1/2 AD7592JN R5 20k VOUT A2 AD544J
18 VDD 19 VREF VIN R1*
20 RFB
AD7545
12
SIGN BIT
*FOR VALUES OF R1 AND R2
SEE TABLE I.
Figure 6. 12-Bit Plus Sign Magnitude D/A Converter REV. A
AD7545
V DD = +5 volts. However, great care should be taken to ensure that the +5 V used to power the AD7545 is free from digitally induced noise. Temperature Coefficients: The gain temperature coefficient of the AD7545 has a maximum value of 5 ppm/C and a typical value of 2 ppm/C. This corresponds to worst case gain shifts of 2 LSBs and 0.8 LSBs respectively over a 100C temperature range. When trim resistors Rl and R2 are used to adjust fullscale range, the temperature coefficient of R1 and R2 should also be taken into account. The reader is referred to Analog Devices Application Note "Gain Error and Gain Temperature Coefficient of CMOS Multiplying DACs," Publication Number E630-10-6/81.
SINGLE SUPPLY OPERATION
+2
+1
DNL - LSB
0
-1
-2 0 5 VDD - Volts 10 15
The ladder termination resistor of the AD7545 (Figure 1) is connected to AGND. This arrangement is particularly suitable for single supply operation because OUT1 and AGND may be biased at any voltage between DGND and VDD. OUT1 and AGND should never go more than 0.3 volts less than DGND or an internal diode will be turned on and a heavy current may flow which will damage the device. (The AD7545 is, however, protected from the SCR latch-up phenomenon prevalent in many CMOS devices.) Figure 7 shows the AD7545 connected in a voltage switching mode. OUT1 is connected to the reference voltage and AGND is connected to DGND. The D/A converter output voltage is available at the VREF pin and has a constant output impedance equal to R. RFB is not used in this circuit.
+15V
18
Figure 8. Differential Nonlinearity vs. VDD for Figure 7 Circuit. Reference Voltage = 2.5 Volts. Shaded Area Shows Range of Values of Differential Nonlinearity that Typically Occur for L, C and U Grades.
0.5
0.0
DNL - LSB
-0.5
-1.0
-1.5
REFERENCE VOLTAGE
1 2
OUT1 AGND DGND
3
VDD
AD7545
VREF 19
VO
-2.0 0 5 VREF - Volts 10
DB11-DB0 12
15 VOLT CMOS DIGITAL INPUTS
Figure 7. Single Supply Operation Using Voltage Switching Mode
Figure 9. Differential Nonlinearity vs. Reference Voltage for Figure 7 Circuit. VDD = 15 Volts. Shaded Area Shows Range of Values of Differential Nonlinearity that Typically Occur for L, C and U Grades.
The loading on the reference voltage source is code dependent and the response time of the circuit is often determined by the behavior of the reference voltage with changing load conditions. To maintain linearity, the voltages at OUT1 and AGND should remain within 2.5 volts of each other, for a VDD of 15 volts. If VDD is reduced from 15 V, or the differential voltage between OUT1 and AGND is increased to more than 2.5 V, the differential nonlinearity of the DAC will increase and the linearity of the DAC will be degraded. Figures 8 and 9 show typical curves illustrating this effect for various values of reference voltage and VDD. If the output voltage is required to be offset from ground by some value, then OUT1 and AGND may be biased up. The effect on linearity and differential nonlinearity will be the same as reducing VDD by the amount of the offset.
The circuits of Figures 4, 5 and 6 can all be converted to single supply operation by biasing AGND to some voltage between VDD and DGND. Figure 10 shows the twos complement bipolar circuit of Figure 5 modified to give a range from +2 V to +8 V about a "pseudo-analog ground" of 5 V. This voltage range would allow operation from a single VDD of +10 V to +15 V. The AD584 pin-programmable reference fixes AGND at +5 V. VIN is set at +2 V by means of the series resistors R1 and R2. There is no need to buffer the VREF input to the AD7545 with an amplifier because the input impedance of the D/A converter is constant. Note, however, that since the temperature coefficient of the D/A reference input resistance is typically -300 ppm/C; applications that experience wide temperature variations may require a buffer amplifier to generate the +2.0 V at the AD7545 VREF pin. Other output voltage ranges can be obtained by changing R4 to shift the zero point and (R1 + R2) to change the slope, or gain, of the D/A transfer function. VDD must be kept at least 5 V above OUT1 to ensure that linearity is preserved. -6- REV. A
AD7545
VDD = +10V TO +15V 18 +2V R1 10K MSB 4 VDD 19 VREF 20 RFB OUT1 1 A1 2 AD544L +5V VDD
DATA
C1 33pF R3 10k
R5 20k
AD7545
DB10-DB0 AGND DGND 3
A2 AD544J
VO
R6 5k R4 33.3k
R2 2k
2
1 8
AD584J 4
Figure 12 shows an alternative approach for use with 8-bit processors which have a full 16-bit wide address bus such as 6800, 8080, Z80 This technique uses the 12 lower address lines of the processor address bus to supply data to the DAC, thus each AD7545 connected in this way uses 4k bytes of address locations. Data is written to the DAC using a single memory write instruction. The address field of the instruction is organized so that the lower 12 bits contain the data for the DAC and the upper 4 bits contain the address of the 4k block at which the DAC resides.
CMOS DATA BUS VDD = +10V TO +15V
A15 16-BIT ADDRESS BUS A0 4
Figure 10. Single Supply "Bipolar" Twos Complement D/A Converter
CPU
ADDRESS DECODE Q0
DB11 12 DB0
MICROPROCESSOR INTERFACING OF THE AD7545
AD7545
CS
The AD7545 can directly interface to both 8- and 16-bit microprocessors via its 12-bit wide data latch using standard CS and WR control signals. A typical interface circuit for an 8-bit processor is shown in Figure 11. This arrangement uses two memory addresses, one for the lower eight bits of data to the DAC and one for the upper four bits of data into the DAC via the latch.
WR
WR
D7 DATA BUS D0
Figure 12. Connecting the AD7545 to 8-Bit Processors via the Address Bus
SUPPLEMENTAL APPLICATION MATERIAL
A15 ADDRESS BUS A0 Q0* ADDRESS DECODE CPU 4 WR WR 8 DB0 D7 8-BIT DATA BUS D0 8 Q1* CS LATCH 4 DB8 DB11
For further information on CMOS multiplying D/A converters the reader is referred to the following texts: Application Guide to CMOS Multiplying D/A converters available from Analog Devices, Publication Number G479.
AD7545
CS
Gain Error and Gain Temperature Coefficient of CMOS Multiplying DACS--Application Note, Publication Number E630-10-6/81 available from Analog Devices.
WR DB7
* Q0 = DECODED ADDRESS FOR DAC
Q1 = DECODED ADDRESS FOR LATCH
Figure 11. 8-Bit Processor to AD7545 Interface
REV. A
-7-
AD7545
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
20-Terminal Leadless Ceramic Chip Carrier (LCCC) (E-20A)
20-Lead Plastic Leaded Chip Carrier (PLCC) (P-20A)
-8-
REV. A
PRINTED IN U.S.A.
C670d-0-6/97
20-Lead Plastic DIP (N-20)
20-Lead Cerdip (Q-20)

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